Accompanied by trend toward multifunction and compactness of various electronic apparatuses, semiconductor devices incorporated in an electronic apparatus leads to such a structure with a lot of built-in circuit elements even with compactness. As a method of improving integration density of a semiconductor device (integrated circuit device), three-dimensional stacked semiconductor device is known.
For example, such a structure of planning intensive integration with LSI chips having through-type electrodes over a plurality of stages stacked and secured on an interposer is proposed (for example, Patent Document 1 and Non-Patent Document 1).
A three-dimensional device with first to third semiconductor substrates stacked to form an integrated circuit is known. In this three-dimensional device, an SOI substrate is used in the third semiconductor device (for example, Patent Document 2).
As technology necessary for manufacturing a three-dimensional stacked LSI, there is technology of forming through-type electrodes in a semiconductor substrate. The current process of forming through-type electrodes in a silicon (Si) wafer still requires a lot of steps (for example, Non-Patent Document 2).
[Patent Document 1]: Japanese Patent Laid-Open No. 2003-46057
[Patent Document 2]: Japanese Patent Laid-Open No. 2001-250913
[Non-Patent Document 1]: The Institute of Electrical Engineers of Japan, Research Reports of Materials Research Society, VOL. EFM-02-6, No. 1-8, P. 31-35
[Non-Patent Document 2]: Journal of the Surface Finishing Society of Japan, VOL. 52, No. 7, 2001, P. 479-483